Senior/Staff or Principal SoC Design Verification Engineer Remote / work from any US location US Citizen or US Permanent Resident Primary Responsibilities Develop test plans, writing testbenches and tests, and debugging any bugs found with the RTL team Develop and execute verification plans for digital designs using SystemVerilog and UVM Create and maintain testbenches, test cases, and test vectors Contribute to the development of novel methodologies and verification techniques Lead technical projects and mentorship of junior team members. Run simulations to verify design against specifications. Analyze results, identify issues, and debug designs Implement coverage tracking and metrics Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies
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Job Type
Full-time
Career Level
Senior