Senior Silicon Design Verification Engineer, YouTube Video Accelerators

Google • Mountain View, CA

16d

About The Position

Be part of a team that pushes boundaries, developing custom silicon solutions
that power the future of Google's direct-to-consumer products. You'll contribute
to the innovation behind products loved by millions worldwide. Your expertise
will shape the next generation of hardware experiences, delivering unparalleled
performance, efficiency, and integration. At YouTube, we believe that everyone
deserves to have a voice, and that the world is a better place when we listen,
share, and build community through our stories. We work together to give
everyone the power to share their story, explore what they love, and connect
with one another in the process. Working at the intersection of cutting-edge
technology and boundless creativity, we move at the speed of culture with a
shared goal to show people the world. We explore new ideas, solve real problems,
and have fun — and we do it all together.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog.

Nice To Haves

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in test planning and testbench architecture using SystemVerilog and UVM, including coverage-driven and constrained random testing.
• Experience with High-Level Synthesis tools (e.g., Catapult, Vivado, XLS).
• Experience in video processing, image pipelines, or video compression standards such as AV1, AV2, or H.264.
• Ability to debug complex issues across C/C++ and RTL levels using industry-standard EDA tools like VCS, Xcelium, or Verdi.
• Excellent C/C++ skills for developing HLS testbenches and models.

Responsibilities

• Lead comprehensive verification strategies and signoff for complex blocks where the source is C/C++, taking full ownership of quality from High-Level Synthesis (HLS) code to generated Register-Transfer Level (RTL).
• Design and maintain advanced environments, including C/C++ GoogleTest for functional validation and SystemVerilog/Universal Verification Methodology (UVM) for RTL timing and system interactions.
• Employ HLS-specific methods such as C/RTL co-simulation, formal equivalence verification, and transaction-level modeling to ensure hardware fidelity.
• Drive complex bug hunting and coverage analysis across both C++ and RTL domains to ensure complete verification of the design transformation.
• Partner with design teams to optimize C++ code for verification and mentor engineers on the nuances of HLS verification.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level