We are seeking a Silicon Pre-to-Post Validation Lead with experience in writing verilog code to join our team. In this dual-capacity role, you will be responsible for both the silicon emulation (pre silicon) to silicon validation of Complementary Metal Oxide Semiconductor (CMOS) backplane. You will also be responsible for post silicon validation specification and execution. You will require an in-depth understanding of Register-Transfer Level (RTL) design, digital verification, and all aspects of micro display validation. Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets. The US base salary range for this full-time position is $227,000-$320,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.