Senior Signal Integrity Hardware Engineer

Arista Networks • Santa Clara, CA

67d • $130,000 - $225,000

About The Position

Arista's cutting-edge Ethernet platforms are built to push the limits of performance, density, and power efficiency. This wouldn't be possible without our Signal Integrity (SI) engineers-who design, simulate, and characterize interconnects enabling the fastest SerDes technologies in the industry. We're looking for a Senior Signal Integrity Hardware Engineer to join our Hardware Design team at headquarters in Santa Clara, CA. In this role, you'll work at the intersection of advanced simulation, next-generation SerDes (112G/224G PAM4), and innovative routing and packaging techniques. Your work will directly influence the architecture and layout of Arista's next-generation Ethernet systems for hyperscale, AI, and cloud networking.

Requirements

• BS/MS/PhD in Electrical Engineering, Physics, or related field with a focus on electromagnetics, signal integrity, or high-speed digital design.
• Solid understanding of signal integrity theory, S-parameter analysis, and channel modeling.
• Hands-on experience with 2.5D/3D EM solvers (Ansys HFSS, SiWave, Sigrity, CST).
• Strong lab skills using oscilloscopes, VNAs, TDRs, BERTs, and Ethernet compliance tools.
• Familiarity with advanced PCB materials (e.g., Megtron 7, Tachyon 100G, SLP) and manufacturing constraints for high-speed design.
• Experience analyzing and simulating 56G/112G/224G PAM4 and NRZ serial links.
• Knowledge of power integrity and co-simulation techniques is a plus.
• Excellent communication and collaboration skills.

Responsibilities

• Perform 3D EM design and simulation of high-speed interconnects (channels, vias, packages, and connectors) for 112G/224G PAM4 SerDes using tools such as Ansys HFSS, SiWave, and Cadence Sigrity.
• Develop and validate test vehicles to characterize next-generation PCB materials, packages, and interconnects.
• Conduct S-parameter and time-domain measurements (VNA, TDR, BERT) to extract channel performance and validate modeling correlation.
• Perform link-level analysis for advanced standards (Ethernet 800G/1.6T, PCIe Gen6/Gen7, CXL) using tools such as Keysight ADS or Cadence SystemSI.
• Collaborate closely with hardware, mechanical, and packaging teams to optimize stack-up, breakout, and routing strategies for high-density designs.
• Research and prototype novel materials, backplane concepts, and low-loss interconnect topologies to meet next-generation performance targets.
• Support bring-up and debug of production boards, working cross-functionally to root-cause SI/PI issues.

Benefits

• Medical insurance
• Dental insurance
• Vision insurance
• Wellbeing programs
• Tax savings and income protection

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Master's degree
• Number of Employees: 1,001-5,000 employees