Quest Global-posted about 1 month ago
$160,000 - $180,000/Yr
Full-time • Mid Level
Onsite • Palo Alto, CA

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries. We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you. Role Overview: Support silicon team to design and develop the RTL microarchitecture that integrates charge-domain Compute-in-Memory (CIM) with high-throughput vector compute and custom logic. You will architect and implement compute pipelines, memory controllers, and high-speed IO subsystems (UCIe, Ethernet, UALink), working closely with SoC architects, software teams, and physical design to ensure scalable and efficient integration.

  • Define and implement RTL microarchitecture for CIM-aware vector/SIMD compute pipelines, DMA engines, and data movement fabrics.
  • Integrate compute units with 3D-stacked CIM dies via custom NoCs with performance and timing constraints.
  • Design RTL for high-speed IO blocks including UCIe, UALink, SerDes, and 800G Ethernet MACs.
  • Collaborate with SoC architects to ensure coherency, cache control, and bus protocols across compute and memory domains.
  • Engage with firmware/software teams to define early validation hooks and develop functional testbenches and bring-up diagnostics.
  • Deliver early microarchitecture models and integration stubs to software/firmware teams for pre-silicon testing.
  • Coordinate with P&R and layout teams to ensure floorplan-aware RTL, proper clocking, and IO placement.
  • 7+ years of RTL design and microarchitecture experience in high-performance SoCs, DSPs, or AI accelerators.
  • Expertise in multi-core compute fabric, pipeline design, and tightly coupled memory subsystems.
  • Proven experience designing and verifying IO logic for UCIe, PCIe, SerDes, or chiplet-based architectures.
  • Strong understanding of SoC-level system architecture, memory hierarchy, coherency protocols, and debug features.
  • Familiarity with early bring-up methodology: RTL-based testbench creation, firmware interface modeling, and diagnostics support.
  • Tools: Verilog/SystemVerilog, UVM (preferred), Synopsys/Cadence synthesis and P&R flow.
  • Exposure to compute-in-memory, near-memory compute, or heterogeneous multi-die integration is highly desirable.
  • 401(k)
  • Dental insurance
  • Health insurance
  • Life insurance
  • Paid time off
  • Referral program
  • Vision insurance
  • Short/Long Term Disability
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