Senior RTL Design Engineer (2026 New College Graduate)
About The Position
About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Summary of Role: We are seeking a experienced Senior RTL Design Engineer to join our silicon development team. In this role, you will architect, design and implement high‑performance digital logic for advanced SoC and IP‑level designs. You will work closely with architecture, verification, physical design, and firmware teams to deliver production‑quality hardware. This position is ideal for an engineer with technical expertise in RTL development, strong problem‑solving skills, and a passion for building industry‑leading silicon.
Requirements
- Education – Bachelor’s or Master’s degree in Electrical or Computer Engineering or related field.
- Experience – 2-4 Years in SoC or IP design.
- Expertise in Verilog and/or the synthesizable subset of SystemVerilog
- Strong understanding of fundamental design concepts.
- Strong understanding of AMBA protocols.
- Excellent debugging skills.
- Experience in an SoC design being taken all the way through to tape-out.
- Fluency in English Language – written & verbal
Nice To Haves
- Experience with CPU, DSP, networking, or security IP blocks.
- Experience automating workflows.
- Working knowledge of Python or other scripting languages.
- Project management skills - i.e., the ability to innovate and execute on solutions that matter; the ability to navigate ambiguity.
- Strong written and verbal communication skills.
- Strong planning & organizational skills.
Responsibilities
- Develop micro‑architecture specifications based on system‑level requirements.
- Implement high‑quality RTL using SystemVerilog.
- Own blocks from concept through integration and tape‑out.
- Optimize designs for power, performance, area (PPA) through architectural improvements and synthesis‑driven iteration.
- Integrate IP blocks into larger subsystems and SoCs.
- Collaborate with backend teams to ensure design closure, timing convergence, and physical feasibility.
- Drive design reviews, documentation, and lifecycle design quality processes.
- Mentor junior engineers and provide technical guidance across the team.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Number of Employees
5,001-10,000 employees
