Senior RFIC Layout Designer

K2 Space

13d • $120,000 - $180,000

About The Position

We are seeking a Senior RFIC Layout Designer to drive the physical implementation of advanced RF and mixed-signal integrated circuits for next-generation satellite communication systems. This is a senior individual contributor role focused on hands-on layout execution and top-level integration, working closely with cross-functional teams to deliver high-performance silicon.

Requirements

• 5+ years of RF/analog/mixed-signal layout experience.
• Extensive hands-on experience with advanced FinFET process technologies (≤16nm preferred).
• Proven track record of top-level SoC layout integration and successful silicon tapeouts.
• Experience collaborating with distributed teams, including collaborating with external layout vendors.
• Deep understanding of RF and analog layout techniques and device physics, including high-frequency effects, parasitics, and isolation strategies.
• Extensive hands-on experience with power planning and full-chip physical architecture.
• Strong proficiency with industry-standard tools.

Nice To Haves

• Experience with high-frequency RF systems for wireless or satellite communications.
• Experience working on large mixed-signal SoCs with significant digital content.
• Exposure to reliability requirements for space or high-reliability applications.
• Experience developing methodologies in a high-growth environment.

Responsibilities

• Execute high-quality layout for RF, analog, and mixed-signal blocks in advanced FinFET nodes (e.g., LNA, RF amplifiers, mixers, PLL, LO generation, ADC/DAC, baseband filters, bandgap/bias/LDO)
• Contribute to top-level layout integration, including block placement, routing, power planning, and floorplanning.
• Contribute to layout strategies to meet performance, area, power, reliability, and manufacturability targets.
• Ensure robust implementation of matching and symmetry for sensitive RF/analog structures, and high-frequency routing and parasitic control.
• Ensure robust implementation of EM/IR, ESD, latch-up, and reliability considerations
• Collaborate closely with RF/analog designers, digital implementation teams, package/PCB engineers, and CAD to ensure seamless integration.
• Participate in establishing review processes (layout reviews, signoff checks, and quality metrics) to ensure first-pass silicon success.
• Drive full-chip physical signoff, including DRC/LVS/ERC closure, EM/IR and reliability verification.
• Own tapeout readiness and interface with foundry and EDA partners as needed.

Benefits

• Base salary range for this role is $120,000 – $180,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed