Senior Reset and Boot ASIC Engineer

NVIDIA • Santa Clara, CA

86d • $136,000 - $212,750

About The Position

NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. With the System-ASIC team, you will contribute to designing multiple products that will be used in a variety of applications from consumer graphics to self-driving cars and the growing field of artificial intelligence. System-ASIC team works closely with System Architecture team on product definitions, implements new innovative flows to improve our chip yield and to address multiple sectors, defines Reset and Boot Architecture and implements them in complex GPU and Tegra chips. The team is also handling the architecture, design, and synthesis of multiple System-level modules.

Requirements

• BS / MS in Microelectronics/ Electronic Engineering/ Computer Science and related (or equivalent experience)
• 5+ years of SoC design/integration experience, including architecture and implementation of system-level functions like Reset or Chip Boot
• Solid frontend ASIC design skills, including RTL design, asynchronous and synchronous Reset design, synthesis, timing analysis, and Spyglass/CDC/RDC checks
• Excellent analytical and problem-solving skills and attention to detail.

Nice To Haves

• Broad knowledge with GPU techniques, SOC architecture, Computer architecture, and ARM/RISC-V CPU
• Experience with general interface protocols such as PCIE, CXL, UCIE, AMBA, and CHI
• Familiar with OCP secure boot specification and physical security handling process
• Possess design experience with cross-die/chipset communication in multi-dielet/chipset systems
• Proficient in Perl/Python scripting

Responsibilities

• Be an integral part of the System ASIC Design team to help with the Micro-architecture definition for system-level functions, including Reset and Boot.
• Collaborate with architects, ASIC designers, and verification engineers to design sophisticated system-level modules such as Floorsweep, In-silicon measurement, Reset and Boot controllers.
• Responsible for the RTL design, logic synthesis, and timing analysis of several modules.
• Integrate modules into the overall SOC design and work closely with other teams in the silicon bring-up process and ensure successful SOC level integration.
• Identify and implement improvements in the current design flow and methodologies to improve efficiency and quality.

Benefits

• Competitive salaries
• Generous benefits package
• Equity eligibility

What This Job Offers

• Career Level: Senior
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees