Senior Product and Test Engineer

Cerebras Systems•Sunnyvale, CA

3d•$175,000 - $275,000•Onsite

About The Position

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include global corporations across multiple industries, national labs, and top-tier healthcare systems. In January, we announced a multi-year, multi-million-dollar partnership with Mayo Clinic, underscoring our commitment to transforming AI applications across various fields. In August, we launched Cerebras Inference, the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. We are seeking a highly experienced Senior VLSI Product and Test Engineer with 10+ years of expertise in semiconductor testing, with a specialized focus on wafer-scale and large-scale AI/ML accelerator testing. The successful candidate will drive test program development for wafer-scale processors, drive innovative test strategies for massive parallel processing units, IOs, and memories. In this exciting role, you will be responsible for ATE strategy for future generations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have depth in testing, characterization of silicon defects, failure modes, and experience delivering end-to-end solutions working closely with teams across chip design, fabrication, validation, production, and manufacturing.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
10+ years of hands-on experience in semiconductor test engineering with a focus on large-scale integration
Proven track record in wafer-scale testing, AI/ML accelerator testing, or large parallel processor/GPUs with SRAM, DDR-DRAM, HBM
Expert-level Advantest 93K experience with Teradyne as an alternative
Experienced in advanced interconnect testing (mesh networks, NoC, high-speed serial links)
Expertise in High-Speed Serdes testing at ATE, package, and system level
Experience in handling analog blocks in large digital ASICs
Expertise in load-board and probe-card specification, design, development, and debug for advanced DFT implementation that comprises boundary scan, scan, BIST, ATPG, and functional tests
Test program development and optimization
Production test debugging, and yield improvement
Good interpersonal skills with the ability & desire to work as a standout colleague and problem solver
Proven track record of working cross-functionally, learning fast, and driving issues to closure
Working knowledge of git repositories, GitHub, git actions/Jenkins, merge and release flows to streamline test and release

Nice To Haves

Proficiency in programming languages: C/C++, Python, Perl for large-scale data analysis
Experience with advanced test data analysis tools and machine learning techniques for yield optimization
Familiarity with advanced packaging technologies for wafer-scale systems (TSV, advanced interconnects)
Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
Knowledge of chip defect profiles and mitigation strategies across manufacturing steps

Responsibilities

Design and develop comprehensive test programs for wafer-scale processors and large-scale AI/ML accelerator chips
Implement sophisticated DFT strategies for wafer-scale designs, including hierarchical scan chains and distributed BIST
Create scalable test methodologies for testing hundreds to thousands of processing cores on a single wafer, with distributed SRAM
Develop fault isolation techniques for identifying defective cores/tiles within wafer-scale processors
Implement efficient wafer-level test flows that can handle massive parallelism and complex interconnect structures such as mesh networks, on-chip NoC, and die-to-die communication
Work with the DFT engineers, silicon architects/designers, performance engineers, and software engineers to enhance the testability of Wafer Scale Engines.
Work refining test programs for di/dt, V-F characterization space, current and temperature limits
Optimize test programs for testing multiple die simultaneously while maintaining test quality
Develop innovative approaches for power delivery and thermal management during wafer-level testing
Develop test strategies for wafer-scale integration-testing, yield optimization, redundancy, and fault tolerance verification
Analyze spatial defect patterns across wafer-scale devices and implement corrective actions