Senior Principal Engineer, Reliability

Marvell Technology•Santa Clara, CA

15h

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Reliability Engineering Team is core part of the Marvell Quality organization and focuses on design for quality/reliability, qualification, reliability testing, supplier enablement and risk analysis of cutting edge products across all of Marvell’s business units. What You Can Expect Lead development of unified reliability sign‑off methodologies for individual IP and full chip tape-outs. Drive cross‑functional alignment with design, technology, packaging, and foundry teams on reliability related rules, limits and assumptions Perform full‑chip EM assessments, including FIT roll‑ups, statistical EM budgeting, and high‑current risk evaluations Define and maintain the company‑wide package Imax specification and guide its implementation across products Lead reliability characterization efforts, including test‑vehicle definition and incorporation of test structures into package builds Establish internal reliability forum to provide best known mitigation techniques, design guidance and structured violation reviews. Serve as foundry/OSAT liaison for EM‑related rules, models, and technology roadmaps Represent the company through conference leadership, standard bodies and invited talks Shape long‑term reliability strategy for future interconnect and packaging technologies, including emerging co-packaged technologies. Evaluate risks and pioneer DFR for advanced packaging solutions, including 2.5D/3D architectures (e.g., CoWoS, EMIB, CPO, CP

Requirements

Bachelor’s or Advanced degree in Physics, EE, Material Sciences, or related field.
Significant industry experience, preferred 15+ years (10+ with a Master’s, 8+ with a PhD)
5+ years of experience in product qualification, design for reliability or related disciplines.
Experience in foundry and packaging manufacturing process, including advanced node and technologies.
Able to develop and define pre-silicon Quality and Reliability requirements with design, packaging and foundry teams.
Participate in problem solving and quality improvement activities.
Excellent communication, presentation, and documentation skills.
Recognized industry expert/publisher in reliability engineering or related technical communities

Responsibilities

Lead development of unified reliability sign‑off methodologies for individual IP and full chip tape-outs.
Drive cross‑functional alignment with design, technology, packaging, and foundry teams on reliability related rules, limits and assumptions
Perform full‑chip EM assessments, including FIT roll‑ups, statistical EM budgeting, and high‑current risk evaluations
Define and maintain the company‑wide package Imax specification and guide its implementation across products
Lead reliability characterization efforts, including test‑vehicle definition and incorporation of test structures into package builds
Establish internal reliability forum to provide best known mitigation techniques, design guidance and structured violation reviews.
Serve as foundry/OSAT liaison for EM‑related rules, models, and technology roadmaps
Represent the company through conference leadership, standard bodies and invited talks
Shape long‑term reliability strategy for future interconnect and packaging technologies, including emerging co-packaged technologies.
Evaluate risks and pioneer DFR for advanced packaging solutions, including 2.5D/3D architectures (e.g., CoWoS, EMIB, CPO, CP