Senior Principal Engineer, Design Verification

Altera-posted 3 months ago
$221,500 - $326,300/Yr
Full-time • Senior
San Jose, CA
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Altera is a leading FPGA (Field-Programmable Gate Array) company that delivers programmable hardware, software, and development tools to drive innovation from cloud to edge. With over four decades of experience in programmable logic, our broad portfolio includes FPGAs, CPLDs, IP, SmartNICs, IPUs, and System on Modules—supported by industry-leading tools like the Quartus development suite. Recently re-established as an independent business (with Intel retaining a minority interest), Altera is focused on accelerating programmable compute in AI, networking, communications, industrial, automotive, aerospace/military, and edge-computing domains. Our mission is to provide leadership programmable solutions that are easy to design and deploy, and our vision is to pioneer innovation that unlocks extraordinary possibilities. We are seeking a highly experienced Senior Principal Engineer, Design Verification to lead the verification of cutting-edge data center and networking silicon solutions. The successful candidate will bring deep technical expertise in PCIe (Gen1–6), host interface subsystems, and high-performance verification methodologies to ensure first-pass silicon success across DPUs, SmartNICs, and HPC platforms. In this role, you will architect scalable verification environments, drive test plans from concept to execution, and provide technical leadership across global teams. You will collaborate closely with architecture, design, and post-silicon validation teams to deliver industry-leading hardware solutions.

  • Lead verification of complex IPs and subsystems, including PCIe Gen5/Gen6 controllers, host interfaces, high-performance DMA engines, datapath accelerators, and fabric interconnects.
  • Architect and implement UVM-based scalable verification environments for next-generation data center hardware.
  • Define and execute comprehensive test plans, ensuring functional coverage and verification closure.
  • Collaborate with design and post-silicon engineering teams to debug and resolve issues across pre-silicon and post-silicon environments.
  • Drive methodology and infrastructure improvements to accelerate coverage closure and reduce verification cycle times by 50% or more.
  • Provide technical leadership and mentorship to junior engineers, and coordinate across global verification teams.
  • Partner with architects to review specifications and contribute to innovative debug features and system performance enhancements.
  • Deliver high-quality, first-pass silicon for data center, HPC, and networking products.
  • Serve as a strategic technical leader influencing verification strategy across multiple programs.
  • Champion best practices in methodology, automation, and infrastructure, driving adoption across engineering teams.
  • Act as a thought leader in PCIe and high-performance SoC verification, representing the company at technical forums, conferences, and standards committees when required.
  • Drive cross-functional alignment across architecture, design, and validation to accelerate product delivery.
  • Mentor, coach, and inspire the next generation of verification leaders, building a pipeline of technical expertise across the organization.
  • Bachelor’s degree in Computer Engineering, Electrical Engineering, or related field.
  • 20+ years of experience in ASIC/SoC design verification.
  • Expertise in PCIe (Gen1-6) protocols, host interfaces, and complex SoC subsystems.
  • Strong proficiency in SystemVerilog, Verilog, UVM, OOP, and testbench development.
  • Proven track record of delivering production-quality silicon in advanced networking and HPC applications.
  • Hands-on experience in debugging pre-silicon and post-silicon issues.
  • Strong leadership experience, with the ability to guide teams of engineers across multiple sites.
  • Master’s degree in Electrical/Computer Engineering or related field.
  • Experience with DPUs, SmartNICs, and high-performance computing (HPC) architectures.
  • Familiarity with encryption engines, checksum/CRC units, ARM interconnects, and fabric switches.
  • Demonstrated success in driving cross-functional alignment under aggressive schedules.
  • Holder of multiple U.S. patents in I/O, debug, or system performance (or equivalent technical innovations).
  • Incentive opportunities that reward employees based on individual and company performance.
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