Senior Principal Engineer - Design For Test (DFT)

Marvell • Morrisville, NC

97d • $170,800 - $252,750

About The Position

As a Digital IC Design Senior Principal Engineer with Marvell, you'll be a member of the Custom Silicon Engineering team. This team is a leader in large multi-die designs that are driving high compute performance and acceleration in many markets, including custom AI, 5G and 6G. The role will be challenging and will require an experienced DFT engineer that can work with existing DFT solutions while also creating new solutions to address industry first issues.

Requirements

• Bachelor's, Master's degree or PhD in Computer Science, Electrical Engineering or related fields with minimum of 15 years of work experience.
• Direct DFT experience with at least 12 years in the custom chip design business.
• Led the DFT execution on several ASICs, responsible for all DFT execution functions from architecture definition to tape out through silicon bring-up.
• Hands-on working experience in various stages of DFT-Execution: SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bring-up/Debug.
• Thorough knowledge on various DFT/Test architecture solutions and involvement in DFT-Architecture definition of at least five monolithic designs.
• Thorough knowledge on various DFT/Test architecture solutions for 2.5D/3D IC design and involvement in DFT-Architecture definition of at least a couple of MCM designs.
• Strong fundamentals in digital circuit design and logic design.
• Understanding of DFT flows and methodologies and experience with Siemens/Synopsys Tool set (Tessent, Spyglass/Tmax, Genus, Modus, NCSim/DC).
• Proven track record of problem solving and innovation to meet challenging design requirements.
• Excellent team player and can work with different function leaders, across different geographies to define and execute the DFT project to completion.
• Excellent communications skill both verbal and written.
• Scripting skills using Python, PERL, Tcl and C-Shell is a plus.

Responsibilities

• Architecting, leading and implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs.
• Defining Design-for-Test architecture, implementing various DFT/DFX features, validation, IP-DFT, STA, pattern generation & post-silicon bring-up and debug for various designs/IPs in Custom/Compute space.
• Mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs.
• Defining and enhancing DFT methodologies and tools to benchmark and enable new methodologies in the domain of DFT/Test.

Benefits

• Flexible time off
• 401k
• Year-end shutdown
• Floating holidays
• Paid time off to volunteer

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Master's degree
• Number of Employees: 5,001-10,000 employees