Senior Principal Emulation Design Engineer

Cadence Systems-posted 3 days ago
$154,000 - $286,000/Yr
Full-time • Senior
San Jose, CA
5,001-10,000 employees
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are seeking a highly skilled Design Engineer to join our Palladium Solutions Development team, to drive the development of full-system design verification environments. This role focuses on developing and integrating and validating high speed interface [Serdes, Chip 2 chip link] based subsystems in Emulation Platforms. Development includes Parallel and Serial models for highspeed interface circuits in analog Mixed Signal Designs and components (PHYs). Integration includes the PHY, Controller / Mac and the Accelerable Verification IP (AVIP) environments on Palladium and Protium . End-to-end verification flow development across a wide range of system components including custom test case developments, validating the bare-metal-driver components in emulation platforms.

  • Lead the design and deployment of PHY logic models for emulation platforms including Palladium and Protium .
  • Develop and maintain end-to-end verification environments , encompassing: System-level models including microcontrollers, memories, NoC (Network-on-Chip), and high-speed communication interfaces Test case generation Interface Circuit Performance Analysis.
  • Contribute to system prototyping for early bring-up and validation of full-system designs.
  • Collaborate with cross-functional teams to ensure seamless integration from simulation to emulation .
  • Optimize designs for multi-clock domain synchronization , area , and performance , with a focus on accuracy vs. runtime trade-offs .
  • Drive innovation in emulatable IP solutions and contribute to the evolution of verification methodologies.
  • Bachelor’s or Masters degree in Electrical Engineering, Computer Engineering, or related field with 7-15 years of experience
  • Strong experience with system-level design and communication standards such as PCIe, UCIe, Ethernet, UALink, DDR, USB, SPI, JTAG, AMBA protocols
  • Proficiency in: Converting Analog Mixed Signal Designs [Parallel and Serial models] to emulation models maintaining functional and bit accuracy, enabling software stack development for configuration, control and status monitoring.
  • SystemVerilog for synthesizable RTL design
  • C and Python for modeling, scripting, and automation
  • Lab debug and test case development
  • Hands-on experience with emulation platforms: Palladium, Protium, Zebu, HAPS, Veloci, FPGA
  • Deep understanding of verification flows and emulation acceleration techniques.
  • Experience building emulatable AVIP solutions
  • Familiarity with end-to-end verification environments from simulation through emulation
  • Experience in system prototyping and bring-up
  • Strong analytical and problem-solving skills
  • Excellent communication and leadership abilities
  • paid vacation and paid holidays
  • 401(k) plan with employer match
  • employee stock purchase plan
  • a variety of medical, dental and vision plan options
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