Senior Physical Design Engineer

Marvell•Burlington, VT

40d•Onsite

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. The Marvell Physical Design team is located in our Burlington, VT office, and has a long history of successful design tapeouts in advanced process nodes. Our team is made up of both newer and more experienced engineers with a broad depth of physical design engineering experience. Being a part of our team will give you a chance to work on many different aspects of the chip design process, while working alongside some of the best engineers in the industry. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor and data center chips in a leading-edge CMOS process technology. This role is based in the Marvell office in Burlington, VT. You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. Relocation will be required. Remote work from a different site is not offered at this time.

Requirements

Bachelor's degree in Computer Science, Electrical Engineering or related fields and at least 1-3 years of related professional experience or Master's degree in Computer Science, Electrical Engineering or related fields or equivalent professional experience in lieu of a formal degree
Expertise in full-chip & sub-hierarchy integration
Experience integrating and taping out large designs utilizing a digital design environment
Good understanding of RTL to GDS flows and methodology
Good scripting skills in TCL/Python
Knowledge of Verilog

Nice To Haves

Experience with Cadence Innovus is preferred

Responsibilities

Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner.
Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools.
Work with RTL design teams to drive assembly and design closure.
Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes.
Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation.

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