Senior Physical Design Engineer, HBM

Micron • Richardson, TX

1d

About The Position

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s High‑Bandwidth Memory (HBM) Digital Design organization is seeking a Digital Physical Design Engineer to drive backend implementation of high‑performance, low‑power digital logic used in advanced memory products. This role owns physical implementation from netlist through GDSII with a strong focus on timing closure, power integrity, congestion reduction, and manufacturability in advanced process technologies. You will collaborate closely with RTL, DFT, CAD, and verification teams to deliver high‑quality physical designs and support aggressive performance, power, and area goals in complex multi‑hierarchy HBM systems.

Requirements

• Strong understanding of RTL‑to‑GDSII physical‑design flows including floorplanning, place and route, clocking, and timing closure
• Experience with hierarchical full‑chip integration, partitioning, and budgeting
• Knowledge of PPA tradeoffs and power‑distribution‑network analysis including IR/EM
• Proficiency in scripting languages such as Tcl, Python, Perl, or Shell for automation
• Bachelor’s degree in Electrical or Computer Engineering with relevant industry experience

Nice To Haves

• Experience working in advanced technology nodes with high‑frequency and high‑density physical designs
• Familiarity with memory, HBM, datapath‑intensive logic, or complex clocking architectures
• Understanding of 3D‑IC, advanced packaging, or process‑technology effects on physical‑design implementation

Responsibilities

• Complete physical build implementation from synthesized netlist through GDSII, including floorplanning, placement, CTS, routing, and physical signoff
• Drive timing closure across multiple modes, corners, and scenarios using industry‑standard STA methodologies
• Identify and resolve congestion, IR drop, EM violations, power‑integrity issues, and timing or power failures
• Develop and optimize floorplans, power‑grid structures, and clock‑distribution strategies for high‑performance and low‑power designs
• Integrate custom analog or hard‑IP macros within a digital‑on‑top flow and achieve timing closure around these blocks
• Partner with RTL and DFT teams to influence partitioning, constraints, and early‑stage micro‑architecture decisions
• Implement and validate low‑power techniques including multi‑voltage domains, power gating, and UPF/CPF‑based power intent
• Automate and enhance physical‑design flows and debug EDA tool issues in collaboration with CAD and vendor teams

Benefits

• We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time-off program and paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees