Senior Photonics CAD Engineer

Nvidia•Santa Clara, CA

48d

About The Position

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Make the choice and join us today! We are now looking for a Senior Photonics CAD Engineer. We are part of the global circuits team at NVIDIA that craft the state-of-the-art GPUs for all applications such as supercomputers, gaming consoles and self-driving cars. Come join us in our mission to Engineer the next generation of outstanding products. Teams are dedicated to the architecture and design of CMOS and Silicon-Photonics high-speed chip interfaces (NVLink, IEEE, PCIE, USB, OIF) and other sophisticated photonic functions. Strong hands-on lab experience with silicon evaluation, debugging, characterization, and bring up.

Requirements

MS in Electrical or Computer Engineering (or equivalent experience)
Minimum 5 years of experience in physical design engineering or photonic IC development, including hands-on EDA flow and tool development.
Solid understanding of all aspects of physical design, including floor planning, integration, clock and power distribution, place-and-route, verification, and layout sign-off.
In-depth expertise in Cadence Virtuoso, Calibre, and other industry-standard EDA tools for custom IC and photonics layout design.
Demonstrated proficiency in programming and scripting languages such as Python, Perl, and SKILL for tool and flow automation.
Strong background in hierarchical design methodologies, top-down integration approaches, and design-for-manufacturing concepts including DFM, yield enhancement, and process constraint checks.
Excellent communicator with the ability to work cross-functionally and support large distributed design teams through flow training and tool support.

Responsibilities

Develop and implement physical design and layout methodologies for integrated photonic devices focused on high-speed optical interconnect and sensing applications.
Architect and advance design flows for photonic integrated circuits (PICs) layout, floor planning, waveguide routing, pCell creation, assembly, and backend verification using EDA tools like Cadence Virtuoso, supporting multiple concurrent projects from design through layout generation and sign-off.
Collaborate closely with device design, layout, foundry technology, and packaging teams to optimize workflows, enhance cross-functional efficiency, and solve complex silicon photonics design problems across different technology nodes.
Drive efficiency improvements in design verification, physical extraction, custom rule writing (DRC/LVS), and silicon validation for photonic and electronic ICs.
Provide training and documentation for design teams, establish best practices for code release, and ensure robust version control and design collateral management.