For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Sr Mixed signal verification engineer.
Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications.
Create behavioural models for analog blocks in accordance with guidelines provided by analog designers.
Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks.
Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models.
Perform and troubleshoot unit-level, cluster-level and top-level simulations of mixed-signal designs.
10+ years of experience
Experience in Behavioural Modelling (BM) of Analog design for digital verification
Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS]
Experience in Verilog/SystemVerilog coding
Experience in Virtuoso Schematics tools
Basic knowledge in Analog design
Experience in UVM
Experience in both Synopsys and Cadence tools is an advantage