Senior Modeling Engineer

Neurophos•Austin, TX

8d•Onsite

About The Position

At Neurophos, listed as one of EE Times’ 2025 100 Most Promising Start-ups, we are revolutionizing AI computation with the world’s first metamaterial-based optical computing platform. Our design addresses the traditional shortcoming of silicon photonics for inference and provides an unprecedented AI engine with substantially higher throughput and efficiency than any existing solution. We've created an optical metasurface with 10,000x the density of traditional silicon photonics modulators. This enables a solution with 100x gains in power efficiency for neural network computing without sacrificing throughput; we've made improvements there, too. By integrating metamaterials with conventional optoelectronics, our compute-in-memory optical system surpasses existing solutions by a wide margin and enables truly high-performance and cost-effective AI compute. Join us to shape the future of optical computing. Location: San Francisco Bay Area or Austin, TX. Full-time onsite position. Position Overview: We are seeking experienced hardware modeling engineers to develop sophisticated functional and performance models that define the next generation of Neurophos chips. You will implement models of novel compute blocks, including optical GEMM engines, SRAM vector processors, and dataflow architectures within our YinYang event-driven framework. This role offers the opportunity to work on cutting-edge hardware that doesn't exist anywhere else while shaping modeling methodology from the ground up.

Requirements

BS, MS, or PhD in Computer Engineering, Electrical Engineering, or Computer Science
5-7+ years of experience in hardware modeling, functional simulation, or performance modeling
Strong C++ programming skills (modern C++17/20/23 preferred)
Experience with hardware modeling frameworks, transaction-level modeling, or event-driven simulation
Understanding of computer architecture fundamentals (pipelines, memory systems, accelerators)
Ability to balance modeling fidelity with simulation speed based on analysis objectives
Strong debugging and validation skills for complex hardware models
Effective communication and collaboration across hardware/software teams
Python proficiency for scripting, analysis, and automation

Nice To Haves

Experience with SystemC, TLM 2.x, or custom event-driven simulation frameworks
Background in accelerator modeling (GPU, TPU, NPU, DSP)
Familiarity with Verilator, SystemVerilog, or RTL co-simulation
Knowledge of memory system modeling (HBM, DRAM, caches)
Understanding of ML workloads and framework internals (PyTorch, TensorFlow)
Experience with performance analysis, profiling, and bottleneck identification
Exposure to power modeling frameworks (McPAT, Cacti)
Background in optical computing, photonics, or analog computing
Experience with trace-driven simulation methodologies

Responsibilities

Implement functional models (fmod) of optical compute engines, vector processors, and memory systems
Develop performance models (pmod) with discrete-event timing and power estimation
Work within the YinYang (libyy) event-driven framework to build modular, reusable components
Design clean abstractions and interfaces between hardware blocks
Integrate with Verilator/SystemVerilog for RTL co-simulation and validation
Build trace infrastructure for both coupled and independent simulation modes
Validate models against RTL and contribute to architectural validation efforts
Collaborate with architects, RTL designers, and software engineers
Optimize simulation performance while maintaining modeling fidelity

Benefits

Competitive compensation, including salary and equity options.
Opportunities for career growth and future team leadership.
Access to cutting-edge technology and state-of-the-art facilities.
Opportunity to publish research and contribute to the field of efficient AI inference.

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