Senior Member of Technical Staff, AI-optimized Memory SoC Microarchitect

Micron Technology • Folsom, CA

6d

About The Position

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-performance memory solutions for AI. In Micron's AI-optimized Memory Architecture organization, we partner closely with customers to design and deliver memory solutions purpose-built for emerging AI systems and applications!
As a Senior Member of Technical Staff in the AI-optimized Architecture team, you will drive the definition of SoC microarchitecture of tightly coupled, high‑performance memory for AI workloads. Apply expert knowledge to analyze micro architectural SoC trade-offs in close collaboration with peer architecture, design, and packaging teams. Drive microarchitecture and early SoC design activities, including definition of IP interfaces (e.g., signals, power delivery), clocking, power sequencing, design-for-test, floorplanning, and specification development.

Requirements

• Experience with advanced packaging building blocks and techniques
• Experience with high performance and efficiency stacked architectures.
• Ability to influence decisions through data-driven analysis and clear communication.
• A Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
• 8+ years of proven industry experience delivering silicon‑demonstrated SoC hardware designs.

Nice To Haves

• Strong foundation in analog and digital circuit design, applied to IP interface requirements, power delivery behavior, and clocking constraints.
• Experience with RTL design with experience developing and maintaining microarchitecture specifications.
• Familiarity with chip-level thermal analysis and power hotspot mitigation strategies.
• Strong experience reasoning about finite state machines, interconnects, and frequency vs. energy/power tradeoffs.
• Experience with synthesis, static timing analysis, and relevant EDA toolsets: Prime Power, Prime Shield, Redhawk, and ICC2.

Responsibilities

• Define SoC microarchitecture, including clocking architectures, power sequencing, power delivery, and signal interfaces.
• Own and drive estimates of and optimizations for full-chip timing, area, performance, power, and energy.
• Define and analyze on-die power delivery networks (PDN), including IR drop budgets and power grid topologies.
• Analyze full-chip thermal implications, including power hotspot identification and mitigation.
• Define DFT architectures (e.g., scan chain topology), and set verification requirements.
• Define SoC floorplans in collaboration with physical designers.
• Compose and maintain clear SoC microarchitecture documentation.

Benefits

• We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time-off program and paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 5,001-10,000 employees