Senior Manager of SerDes Design and Build Leads a team of engineers responsible for design, physical implementation, and delivery of high-speed SerDes IP (e.g. 200G/400G, PCIe Gen 7) that is used in our custom ASIC designs. Team’s responsibilities include macro definition, RTL development, timing constraints development, verification co-definition, synthesis, timing analysis/closure, formal verification, place and route, documentation, generating deliverables, and delivering IP to internal and external customers.
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Job Type
Full-time
Career Level
Manager
Number of Employees
5,001-10,000 employees