Senior Manager High Speed Analog Design

Advanced Micro Devices, Inc.•San Jose, CA

48d•Onsite

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD seeks a passionate, collaborative leader with strong technical skills and the initiative to motivate an expert team. You will manage an Analog Design Engineering group and innovate with internal teams and external partners to create the next generation of high speed IO technologies. THE PERSON: The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills.

Requirements

Analog/Mixed signal design lead with professional experience in the semiconductor industry with focus on analog/mixed signal silicon IP design and development.
Experience successfully leading small to medium size analog/mixed signal design engineering teams. Able to lead a team effectively, with good interpersonal skills, enthusiasm and positive energy. Analytical thinking, inventive, and Quality-oriented mindset. Strong and effective technical and management communication at the peer and upward management levels.
Hand-on design experience in high-speed serial and/or parallel (memory, die-to-die interfaces) PHY/IO designs. Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking (PCIE, USB,…,LPDDR, HBM, gDDR, …, UCIE, …)
Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm nodes with a solid understanding of transistor device performance and fundamentals
A track record of successful design and productization of analog/mixed signal silicon IPs.
Direct hands-on experience in the following PHY/IO-AFE/PLL/Clocking circuits architecture and design. In-depth knowledge of analog, digital, and semi-digital circuit architecture
Experience in high-speed custom digital and low power design techniques is highly desirable.
Knowledge of AMS EDA industry-standard tools and best-in-class design practices/methodologies for analog/mixed signal design. Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture/virtuoso, Spectre/HSPICE/other circuit simulation tools
Excellent written and verbal communication skills able to operate without direct supervision but also work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic environment.
Strong initiative and ownership. Seek help proactively as well as share and pass on knowledge

Responsibilities

Lead and manage a team of analog/mixed signal silicon designers for High Speed IO/SerDes/DDR designs (Mixed Signal IPs = MSIP)
Responsibilities high level planning, work breakdown planning, tasks assignments and progress tracking, schedule and priority management, performance review, mentor, talent development, and hiring.
Work with project-manager, system architects, SOC designers and physical designers to guarantee quality/timely deliverables meeting schedule and technical requirements
Contribute to the definition of microarchitecture and circuit architecture for various MSIP & AMS blocks.
Drive various domains (e.g. Analog Design, Custom Digital Design, AMS Circuit Architecture and AMS Design Verification, Layout) across different geographies and time zones, to ensure successful cross-team engagement and high-quality execution
Ensure quality of work within schedule and mitigate overall risk.
Proven Track record of successfully taking high speed IO MSIP designs to production
Contribute to the definition of flows that improve efficiency and quality of execution
Manage circuit verification flows to confirm design meets performance, power, reliability and timing requirements.
Work closely with the mask design organization to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution
Influence development of AMS design workflows and methodology for best in-class/best PPA circuits designs.
Support Post-Silicon teams' activities in validation and characterization of IP (Performance, Power, Functionality, ..)