Senior Manager, ASIC / SoC Design Engineering

Advanced Micro Devices, Inc • San Jose, CA

10h • Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

AMD is seeking a highly motivated and collaborative Silicon Engineering leader with strong technical depth and a passion for building high-performing teams. In this role, you will lead a team of design engineers to deliver next-generation SoC and compute technologies, working closely with cross-functional internal teams and external partners.
This is a high-visibility position requiring both technical excellence and organizational leadership. You will drive microarchitecture development, oversee RTL implementation, and ensure seamless integration of internal and third-party IP. You will be accountable for design quality, functional correctness, and readiness for synthesis and tapeout.
Additionally, you will play a key role in defining and evolving SoC design methodologies, development processes, and best practices to enable future program success.

Requirements

• Engineering
• Digital design and experience with RTL design in Verilog/System Verilog
• Solid understanding of DFT technologies and some experience with execution of DFT flows
• Experience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
• Experience in specifying timing constraints with several clock domains and modes
• Basic experience with Synopsys Design Compiler and Primetime
• Experience designing with multiple power domains and islands using UPF
• TCL, Python, Perl scripting
• Version control systems such as Perforce, IC Manage or Git
• Understanding of FPGA architecture and implementation flow
• Fluent in working with Linux and Windows environment
• Leadership/Management
• Proven background in managing design engineers, cross-functional teams, and delivering excellent results
• Strong verbal and written communication skills
• Ability to organize and present complex technical information
• Project planning and management of execution from Microarchitecture to Timing Closure with engineers in multiple time zones
• Team building experience
• Bachelors or Masters degree in computer engineering/Electrical Engineering

Responsibilities

• Lead a high-performance engineering team through different phases of projects such as Requirements gathering, Project Planning, Project Execution and reporting of key metrics, Design reviews around feature and quality, Stakeholder management, Tapeout readiness, Retrospectives and project wind-down.
• The candidate will also have responsibilities towards building and managing the team from HR perspective (hiring engineers, coaching engineers, growing capabilities, retaining engineers).
• Improve processes for team through AI adoption and traditional automation

What This Job Offers

• Job Type: Full-time
• Career Level: Manager
• Number of Employees: 5,001-10,000 employees