Senior Manager, ASIC Design

Celestial AI-posted 29 days ago
$205,000 - $235,000/Yr
Full-time • Manager
Onsite • Santa Clara, CA
101-250 employees
Publishing Industries
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As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system's interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI's Photonic Fabric is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions. The Photonic Fabric is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies. This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers. ABOUT THE ROLE We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to-end design and development of high-performance ASICs, ensuring technical excellence, on-time project delivery, and alignment with company goals. This role demands proven technical expertise in advanced ASIC design flows and leadership in execution, scheduling, cross-functional coordination, and final product delivery.

  • Lead a team of high performing ASIC design engineers responsible for RTL design of IPs, subsystems and SOCs supporting Celestial AI's photonic fabric roadmap.
  • Develop project schedules, define milestones, allocate resources, manage budgets and ensure timely delivery of high-quality designs that meet product functional and performance goals.
  • Provide technical leadership in defining IP/SOC microarchitecture specifications, and design methodologies. Conduct design reviews to ensure adherence to best practices.
  • Guide the team in optimizing the design to meet aggressive performance, power and area goals using advanced architectural and design techniques.
  • Drive effective and seamless collaboration with partner teams across architecture, verification, physical design, firmware, DFT, and post silicon domains to ensure successful system level functionality.
  • Mentor the team, foster a culture of continuous learning and actively help with career development.
  • Interface with external IP vendors, foundries and EDA tool providers to ensure dependencies and roadblocks are addressed in timely fashion to support team deliverables.
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Minimum of 8+ years of ASIC/SOC digital design experience and 3+ years of people management experience.
  • Excellent leadership, communication, team building and stakeholder management skills.
  • Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
  • Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies.
  • Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
  • Hands on design experience in one or more industry standards/protocol stacks such as CXL, PCIe, HBM, UCIe, UALink etc.
  • Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).
  • Proficiency with front end development tools/methodologies, and scripting for automation and flow integration.
  • PhD in Electrical Engineering, Computer Engineering, or a related field.
  • Experience managing relationships with external design partners, IP vendors, and foundries.
  • Knowledge of Design-For-Testability, post silicon debug/validation/manufacturing test.
  • health
  • vision
  • dental and life insurance
  • collaborative and continuous learning work environment
  • chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing
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