Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below! Life at Intel Intel Global Diversity and Inclusion WHO WE ARE: We are a Custom IP and Silicon engineering team part of Intel's Silicon Engineering Group. The team works on design and verification of cutting edge IP and SoCs geared towards Intel's advanced Data center and AI SoCs. We look to drive major technological and methodological advancements across multiple areas of IP and SoC Design and Verification, looking to set a high bar across the organization and ensure that Intel has a competitive product in the market. WHO YOU ARE: As an IP Logic Design Engineer your responsibilities will include but are not limited to: Designing and/or integrating IP for Intel's Custom Silicon solutions. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation. Creating a design to produce key assets that help improve product KPIs for discrete graphics products. Working with SoC Architecture and platform architecture teams to establish silicon requirements. Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule. Creating micro architectural specification document for the design. Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs. Driving vendor's methodology to meet world class silicon design standards. Architecting area and power efficient low latency designs with scalabilities and flexibilities. Power and Area efficient RTL logic design and DV support. Running tools to ensure lint-free and CDC/RDC clean design, VCLP. Synthesis and timing constraints. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
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Job Type
Full-time
Career Level
Mid Level
Number of Employees
5,001-10,000 employees