About the position
We are now hiring for a Senior Library Design Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a 'learning machine' that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life's work, to amplify human imagination and intelligence. Make the choice, join our diverse team today. The Advanced Technologies Group is looking to hire a Library Design Engineer in our group. Do you have a proven EE background with an in-depth understanding of circuits, simulation, library characterization and static timing analysis? Enjoy working on the cutting edge of process technologies? Have strong programming skills? If you answered yes to all above, then we have a job that might be a good fit for you! The job will be at our company headquarters in Santa Clara, CA.
Responsibilities
- Characterize standard cell libraries for advanced process technologies
- Develop and support extraction environments for standard cell characterization
- Develop flows to generate standard cell IR and thermal views
- Analyze tradeoffs between different standard cell architectures
- Collaborating with cross functional teams to drive PPA targets and provide guidance
- Analyzing foundry device models & layout dependent effects, collaborate with device group for spice to silicon correlation
- Automate characterization flows, model evaluation and publishing process to improve efficiency
- Validate aging and self-heating effects of device models
Requirements
- B.S or M.S. in Electrical Engineering or equivalent experience
- 5+ years industry experience
- An understanding of transistor device behavior, layout dependent device behavior, aging and self-heating effects on advanced FinFET and GAA process nodes
- Strong background in Standard cell design and layout on advanced process nodes
- Hands-on experience with standard cell timing, power, statistical characterization and modeling. Familiar with advanced variation modeling techniques
- Strong experience with gate level spice simulations, variation analysis and parasitic extractions
- Experience with industry standard layout/schematic editor, physical verification, timing characterization and parasitic extraction tools
- Excellent programming skills
- Scripting experience with Perl/Python. Layout automation with Cadence Skill is an additional advantage. Familiarity with debugging timing reports
- Great interpersonal skills
- A passion for working closely with foundry partners and providing excellent support for end-users
Benefits
- Equity
- Benefits
