Semiconductor Components Industries-posted 10 months ago
Senior
Richardson, TX
Computer and Electronic Product Manufacturing

onsemi (Nasdaq: ON) is driving energy efficient innovations, empowering customers to reduce global energy use. The company is a leading supplier of semiconductor-based solutions, offering a comprehensive portfolio of energy efficient power and signal management, logic, standard and custom devices. The company's products help engineers solve their unique design challenges in automotive, communications, computing, consumer, industrial, medical and military/aerospace applications. onsemi operates a responsive, reliable, world-class supply chain and quality program, and a network of manufacturing facilities, sales offices and design centers in key markets throughout North America, Europe and the Asia Pacific regions. onsemi's Central IP Engineering organization is responsible for the selection, acquisition, design, verification, integration and support of reusable intellectual property (IP) that is then used to facilitate custom ASIC and ASSP developments. We are seeking experienced I/O design engineers to join the Central IP‘s Foundation IP team in our Richardson, Texas office.

  • Create I/O specifications from customer library requests and perform feasibility studies of established specifications
  • Develop I/O cells and libraries - General Purpose, LVDS, I2C, I3C, High Voltage, analog, and low power
  • TLP testing of ESD primitives to verify proper ESD protection of I/Os in new technologies
  • Design ESD I/O structures that meet industry standards
  • Transistor and block level CMOS I/O circuit design
  • Functional verification using the latest CAD tools
  • Assist team members during view/model development (physical and front-end views)
  • Supervision of layout and post-layout verification working with layout designers
  • Instruct layout designers how to create layout from schematics to minimize ESD & latch-up problems
  • Review and approval of layout during development
  • Train/mentor junior colleagues
  • Silicon prototype lab evaluation and whole IO debug support
  • Customer support
  • Assist in creation of I/O Roadmap
  • Benchmarking of onsemi I/O libraries and cells with industry competitors
  • University degree in Electrical Engineering or related field; Bachelor minimum and Master preferred
  • 7-10 years of silicon proven experience designing I/O cells circuitry to develop state of the art solutions
  • Hands-on experience with industry standard design and verification tools (e.g. Cadence, Mentor, …)
  • Experience with I/O ESD design and verification
  • Have a strong desire to learn and contribute to an important role in onsemi ASIC development
  • Able to work with a group of engineers inside and outside of the country
  • Ability to automate tasks to raise standards of excellence in product release quality
  • Lead I/O test chip creation and silicon validation
  • Written and verbal communication skills in English at B2 level at least
  • Eligibility to work in the United States and Travel if necessary
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