Senior FPGA Design Engineer

AERONIX INC • Melbourne, FL

5d • Onsite

About The Position

We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop the architecture, implementation, and verification of complex, high-speed FPGA solutions. The ideal candidate will have deep expertise in high-bandwidth interfaces such as PCIe Gen4/5, 10 to 100G+ Ethernet, and DDR4/DDR5, along with strong skills in RTL design (VHDL/Verilog/ SystemVerilog), timing closure, and signal integrity. Experience with Cryptography, DSP and RF applications is strong plus. This role involves driving FPGA design from concept through production, integrating vendor IP, optimizing for low latency and high throughput, and performing rigorous verification and lab validation. The engineer will collaborate across hardware and software teams, mentor junior engineers, and ensure designs meet stringent reliability and compliance standards.

Requirements

• Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration.
• Strong experience in testbench development, functional coverage, and verification of complex FPGA designs.
• Proficient with FPGA simulation and synthesis tools (e.g., QuestaSim, ModelSim, Riviera-PRO, Xilinx Vivado, Intel Quartus).
• Proficiency of FPGA architecture and optimization techniques for timing closure, floor-planning, and resource utilization.
• Ability to perform FPGA power estimation and analysis using vendor tools and optimize designs for power and thermal constraints.
• Strong understanding of high-speed interfaces (PCIe, Ethernet, Serial RapidIO, DDRx) and control protocols (I²C, SPI, RS-232/422).
• Experience with System-on-Chip technologies.
• Bachelor’s Degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum 10 years of relevant experience in FPGA design.
• Excellent written and verbal communication skills.
• Ability to work in a collaborative team environment.
• US Person required; ability to obtain and maintain a DoD Secret clearance.
• Position located in Melbourne, FL or Greenville, SC (not remote).

Nice To Haves

• Proficiency in FPGA Block Design development and debugging (e.g., Vivado, Libero).
• Familiarity with Universal Verification Methodology (UVM).
• Familiarity with Microsemi Libero and Lattus Diamond.
• Familiarity with revision control systems (Git/Bitbucket) and scripting in Python, TCL, or Linux shell for automation.
• Skilled in FPGA lab validation using oscilloscopes, logic analyzers, and protocol analyzers.
• Support JTAG Boundary scan design and testing
• Experience with Cryptography, Digital Signal Processing and RF Applications
• MATLAB modeling
• Strong oral and written communication skills, with ability to document and present technical work clearly.
• Experience collaborating in Agile environments and using tools like Jira and requirements management systems (e.g., Jama).
• Familiarity with Manufacturing processes, and Electronic Stress Screening.
• Understanding of formal verification processes and compliance standards.

Responsibilities

• Lead full life-cycle FPGA development, from requirements and architecture through RTL implementation (Verilog/VHDL), verification, and system integration across multiple FPGA families.
• Define and document FPGA architecture, including block diagrams, clocking strategies, and trade-off analyses; participate in and conduct design reviews.
• Develop robust, reusable, and self-checking testbenches; implement functional coverage models and achieve code coverage closure.
• Create and execute detailed test plans, procedures, and reports; ensure verification rigor and traceability.
• Collaborate with hardware and software teams to integrate FPGA designs at the board and system level; support lab bring-up, debug, and qualification testing.
• Implement and validate JTAG boundary scan and other DFT features; ensure compliance with design-for-test and reliability standards.
• Drive continuous improvement in design practices, coding standards, and verification methodologies; mentor junior engineers and contribute to technical reviews.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level