Senior FPGA Engineer III

Comtech Telecommunications Corp-posted about 1 month ago

Full-time • Mid Level

Onsite • Chandler, AZ

Administrative and Support Services

Resume

Match Score

Senior FPGA Designer with experience in the entire design flow for complex FPGA's.

Design, develop, document, debug and test FPGA SoC systems; including:
IP Integration into FPGA Projects (synthesis/implementation)
High-Performance FPGA IP (VHDL/SystemVerilog)
Userspace Drivers for FPGA IP (C++)
Firmware for Embedded Microcontrollers (C)
Utilize strong communication skills to effectively work and communicate with team members and engineering management.

Strong digital design engineer with FPGA/ASIC SoC design experience
Strong FPGA Implementation with Altera Quartus or Xilinx Vivado
Experience designing/debugging SoC systems with AMBA-compliant AXI and APB interfaces
Experience designing fmax-optimized, high-throughput, pipelined AXI-Stream IP
Capable of creating RTL simulations to identify and resolve most issues before hardware tests
Knowledgeable in Static Timing Analysis (STA) and Synopsis Design Constraints (SDC)
Experience analyzing STA reports and post-synth netlist/placement to resolve failing paths
Experience contributing to schematic capture and layout for FPGA portions of PCB designs
Experience implementing at least one Gigabit Transceiver Protocol:
PCI Express, Interlaken, USB SuperSpeed
1000BASE-X/SGMII, 10GBASE-R, 40GBASE-4, 100GBASE-R4
Experience implementing Network Protocols, such as:
L1: IEEE 802.3, Cisco, Q/SFP+ MSA standards for Ethernet (1G to 100G)
L2/L3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP
L4: VITA 49.2, IEEE-ISTO 4900 Digital IF Interoperability Standard (DIFI) and/or eCPRi
Proficient in SW development with C, C++ and GIT version control
Proficient in Microsoft Office Tools (Word, Excel, PowerPoint, Visio, etc.)
Demonstrated experience supporting multi-disciplinary, cross functional and matrixed teams
5+ years of FPGA/ASIC SoC design experience.

Working knowledge of digital IF streams such as VITA 49.2, DIFI and/or eCPRi (Highly Desired)
Working knowledge of Embedded Linux: Kernel / Yocto / U-Boot / DeviceTree
Working knowledge with SATCOM waveforms like DVB-S2X and/or 5G NTN 3GPP Rel 17/18
Working knowledge of communication networks and security within a zero-trust environment
Experience with Partial Reconfiguration/DFX or PCIe CvP
Possess an active DoD clearance or demonstrate readiness to obtain one

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