Senior Engineering Manager - HAMR Wafer Process Development

Seagate TechnologyBloomington, MN
5dOnsite

About The Position

You will have an exciting opportunity to work on cutting edge technologies, advancing the areal density of Seagate recording heads beyond that of any competitor in the world. This is a Senior Engineering Manager position in our wafer process development team. Our team's mission is to develop new processes for state-of-the-art recording head technology. Recording head process technology encompasses all disciplines employed in semiconductor wafer processes technology, performed in a clean room environment.About the role - you will: Lead a team of highly skilled engineers and technicians responsible for the development and qualification of light-deliver (LD) and magnetic pole (MP) processes for next generation HAMR products. Manage a group of ICP, CMP, and optical test engineers to deliver unit process solutions for HAMR writer. Work with WW ICP and CMP process partner groups to define next-gen tooling to enable process roadmap. Define and execute optical test and tooling technology roadmap to meet the product roadmap requirement. Partner with other NWPD teams to implement, develop, and optimize advanced LD and MP fabrication processes, including lithography, materials, deposition, thin films, and metrology. Direct team resources to implement process changes, reducing wafer content and decreasing cycle time. Manage technology lifecycle from concept to volume launch, partnering with WW wafer production teams to transfer technologies to factory. Work with design team to define and execute roadmaps for device technologies and wafer process in alignment with the HDD roadmap. Align team objectives with organizational goals, driving schedules and deliverables. Oversee technology staging and intellectual property portfolio generation.

Requirements

  • Self-motivated and independent, with a strong work ethic and attention to detail.
  • Proven ability to lead teams with diverse background, manage complex projects, and deliver results on schedule.
  • Demonstrated experiences in wafer process integration.
  • In-depth knowledge of process modules such as CMP, optical test, and plasma etch.
  • Skilled at balancing day-to-day execution needs with long-term strategical planning.
  • Adept at managing cross-functional and cross-team collaborations.
  • Strong written and verbal communication skills, with the ability to explain complex concepts in simple terms.
  • Bachelor's Degree in Science and Engineering-related field, such as Physics, Materials Science & Engineering, Electrical Engineering, Chemistry, Chemical Engineering, or Mechanical Engineering, and 12+ years of experience, or Master's degree in Science and Engineering-related field, such as Physics, Materials Science & Engineering, Electrical Engineering, Chemistry, Chemical Engineering, or Mechanical Engineering, and 8+ years of experience, or PHD and 5+ years of experience or equivalent education and experience.
  • Expertise in wafer process development and integration for recording head fabrication.
  • Hands-on experience in wafer processing, including CMP, plasma etch, and/or thin film process.
  • Demonstrated success in LD and MP module development and transitioning concepts to M1 maturity.
  • Strong statistical data analysis skills and a solid understanding of DOE for wafer process development.
  • Leadership experience either in project management or team lead roles.

Nice To Haves

  • Understanding of the fundamentals and applications of optical test and plasmonics.

Responsibilities

  • Lead a team of highly skilled engineers and technicians responsible for the development and qualification of light-deliver (LD) and magnetic pole (MP) processes for next generation HAMR products.
  • Manage a group of ICP, CMP, and optical test engineers to deliver unit process solutions for HAMR writer.
  • Work with WW ICP and CMP process partner groups to define next-gen tooling to enable process roadmap.
  • Define and execute optical test and tooling technology roadmap to meet the product roadmap requirement.
  • Partner with other NWPD teams to implement, develop, and optimize advanced LD and MP fabrication processes, including lithography, materials, deposition, thin films, and metrology.
  • Direct team resources to implement process changes, reducing wafer content and decreasing cycle time.
  • Manage technology lifecycle from concept to volume launch, partnering with WW wafer production teams to transfer technologies to factory.
  • Work with design team to define and execute roadmaps for device technologies and wafer process in alignment with the HDD roadmap.
  • Align team objectives with organizational goals, driving schedules and deliverables.
  • Oversee technology staging and intellectual property portfolio generation.

Benefits

  • eligibility to participate in discretionary bonus program, medical, dental, vision, and life insurance, short-and long-term disability, 401(k), employee stock purchase plan, health savings account, dependent care, and healthcare spending accounts
  • paid time off, including 12 holidays, flexible time off provided pursuant to Seagate policy, a minimum of 48 hours of paid sick leave, and 16 weeks of paid parental leave
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