Senior Engineer II-Verification

Microchip Technology Inc.Gresham, OR
2d

About The Position

Microchip is seeking a highly skilled and experienced Senior Verification Engineer to join the Advanced Engineering Services team at our Fab 4 facility in Gresham, Oregon. The successful candidate will be responsible for leading the development and implementation of comprehensive verification plans to ensure optimal functionality of our manufactured devices.

Requirements

  • MS degree in EE/CE with 5+ years of industry experience or B.S degree in EE/CE with 7+ years of industry experience preferably in ASIC or FPGA environments.
  • Proficient in HDL languages SystemVerilog, Verilog and VHDL.
  • Apply UVM based verification using coverage driven verification techniques.
  • Hands-on experience with assertion-based verification (ABV), including writing and debugging SystemVerilog Assertions (SVA).
  • Experience with formal verification and assertion analysis tools such as Fishtail, JasperGold, or similar.
  • Familiarity with the Linux compute environment.
  • Excellent analytical and problem-solving skills.
  • Ability to clearly express complex design concepts and simulation results, both verbally and in written form.
  • Proactive and able to work independently or as part of a team.
  • Experience with using scripting languages (Python, Perl, Tcl) for automation.

Nice To Haves

  • Object Oriented programming
  • Understanding of ASIC designs and verification methodologies
  • Domain Expertise : AHB, AXI, PCIe.
  • Experience with additional simulation tools (e.g., VCS, ModelSim)

Responsibilities

  • Develop verification test plans from design specifications.
  • Build verification environments for chip/module level designs using SystemVerilog with UVM.
  • Develop test cases using transaction based checkers to execute verification test plans.
  • Manage and Launch regressions using Cadence tools such as Verisium Manager and Xcelium Simulator.
  • Interpret simulation results using tools such as Simvision to root cause discrepancies between expected and simulated results in collaboration with the design team.
  • Generate and analyze code and functional coverage to ensure adherence to the test plan.
  • Promote and apply advanced verification techniques including constrained random generation, functional coverage, assertions, and formal verification.
  • Work with CAD team to resolve tool related issues and provide test cases, as required.

Benefits

  • We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments.
  • In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature.
  • Find more information about all our benefits at the link below: Benefits of working at Microchip
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