Ciena Government Solutions-posted 5 days ago
Full-time • Mid Level
Rochester, NY
5,001-10,000 employees

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute as a Senior Digital Verification Engineer: The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital verification engineer who will be involved in the verification of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a senior digital verification engineer will be to propose and implement innovative verification strategies, in order to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products based out of Pittsford, New York office. As a senior digital verification engineer, you are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects You are held responsible for the complete and thorough validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods You are expected the create the verification, functional coverage and formal verification test plans You are accountable for the creation of testbench environment and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable You will perform coverage driven verification, monitor regressions and debug resulting failures with the help of the function's designer You are expected to report on status updates on a regular basis

  • Propose and implement innovative verification strategies
  • Thoroughly simulate and validate functional blocks and subsystems
  • Read and understand the architecture and functional requirements specification document(s)
  • Communicate and collaborate with systems engineers and architects
  • Complete and thorough validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods
  • Create the verification, functional coverage and formal verification test plans
  • Creation of testbench environment and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable
  • Perform coverage driven verification, monitor regressions and debug resulting failures with the help of the function's designer
  • Report on status updates on a regular basis
  • Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc or MEng/MSc level
  • A highly motivated self-starter, able to work independently, while being a team player
  • Ability to methodically solve complex technical problems
  • Excellent organization, written and oral (English) communication skills
  • Proficiency above the intermediate level with the use of System Verilog, SVA, and simulators from major vendors.
  • Proven ability in determining appropriate and comprehensive digital verification and coverage strategies
  • Experience with UVM.
  • Experience with formal verification methods
  • Experience in DSP and/or Forward Error Correction
  • Experience with mixed-signal design validation
  • Experience with standards and protocols such as OTN, B100G, Ethernet
  • Experience with using Jira for bug tracking and GIT for source code management and revision tracking
  • Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++, System C
  • medical, dental, and vision plans
  • participation in 401(K) (USA) & DCPP (Canada) with company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • company-paid holidays
  • paid sick leave
  • vacation time
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