Credo Technology Group Ltd.-posted about 2 months ago
$140,000 - $170,000/Yr
Full-time • Mid Level
San Jose, CA
501-1,000 employees
Computer and Electronic Product Manufacturing

We're looking for a Senior Digital Design Engineer to lead front-end ASIC design efforts, including architecture, implementation, and verification of complex logic blocks. You'll collaborate across design, verification, and physical teams to ensure successful tape-outs, while contributing to microarchitecture specs, IP integration, and chip bring-up. This role combines technical depth with cross-functional teamwork to deliver high-performance digital solutions.

  • Write microarchitecture and/or design specifications.
  • Architect/design, implement, and debug complex logic blocks.
  • Understand and integrate complex IPs from internal and external IP vendors.
  • Support all front-end integration activities like Lint, CDC, Synthesis, and ECO.
  • Develop functional tests/testbenches and run functional RTL and Gate-Level verification/simulations.
  • Work with other ASIC Design/Verification, DFT and Physical Design Engineers in achieving a successful tape out.
  • Collaborate with Software, Firmware, Applications, and Systems teams to ensure a high-quality product.
  • Bring-up, validate, and debug functional features in the chip.
  • BS or MS in Electrical Engineering, Computer Engineering, or related field with 5-10 years of experience in digital ASIC design
  • Strong understanding of digital logic design, including synchronous and asynchronous interfaces
  • Proficiency in Verilog/SystemVerilog RTL design
  • Develop functional tests/testbenches and run functional RTL and Gate-Level verification/simulations.
  • Familiarity with UVM methodology
  • Hands-on experience with gate-level simulations, chip bring-up, and validation
  • Knowledge of synthesis and static timing analysis
  • Proficiency in scripting languages such as Python, Tcl, Perl, or Shell
  • Strong planning and estimation skills
  • Effective communicator and collaborative team player
  • This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.
© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service