Senior DFX Methodology Engineer

Nvidia • Santa Clara, CA

66d • $136,000 - $212,750 • Hybrid

About The Position

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a 'learning machine' that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life's work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

Requirements

• BSEE or equivalent experience with 3+ years of experience, MSEE (or PhD) with proven experience in DFT or related domains.
• Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools.
• Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs.
• Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.
• Knowledge of DFT security and hardware system security is a plus.
• Strong programming and scripting skills in Perl, Python or Tcl desired.
• Exceptional written and oral interpersonal skills with the curiosity to work on rare challenges.

Responsibilities

• Own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, IO BIST, memory BIST, scan and array dump and DFX security methodology.
• Help architect, develop and deploy DFT methodologies for our next generation products.
• Mentor junior engineers on test designs and trade-offs including cost and quality.

Benefits

• Highly competitive salaries
• Comprehensive benefits package
• Equity eligibility

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Master's degree
• Number of Employees: 5,001-10,000 employees