Senior Design Verification

Cerebras Systems-posted 4 months ago

Senior

Sunnyvale, CA

Computer and Electronic Product Manufacturing

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In this role, you will play a pivotal part in shaping the future of AI/ML hardware by leading the end-to-end verification of a key block within our next-generation AI/ML accelerator. You will work closely with top talent across cross-functional teams including architecture, design, physical design, and software to ensure the highest quality of our products. As the senior verification member, you will be responsible for driving comprehensive verification strategies from block-level simulations through post-silicon validation. This includes leveraging a variety of methodologies, tools, and environments to ensure robust and efficient verification coverage. As a senior team member, you will mentor junior engineers and provide technical leadership across projects. Your insights will directly influence project planning, feature definition, verification methodologies, and schedules, playing a key role in shaping both the verification organization and the company's product roadmap.

Own and drive the end-to-end verification of a critical IP block from early planning to post-silicon validation for high-performance AI/ML chip.
Define and implement verification strategy, test plans, coverage metrics and methodologies tailored for AI-specific computation and dataflow.
Develop and maintain constrained-random and directed testbenches using industry-standard methodologies (e.g., UVM).
Collaborate with cross-functional teams including architecture, RTL design, physical design, firmware, and validation.
Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases.
Continuously enhance verification infrastructure and flows to improve efficiency and quality.
Review design and architecture specifications to ensure functional correctness and testability.
Mentor and guide junior team members on technical issues and professional development.
Provide regular updates and strategic input to leadership on progress, risks, methodology, and resourcing needs.
Contribute to the evolution of the overall verification methodology and best practices across the organization.

10+ years of Design Verification experience.
Deep knowledge of SystemVerilog language and UVM testbenches.
Experience developing scalable and portable testbenches and components.
Experience working on block and full chip verification.
Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations.
Proficient in a scripting language such as Python.
Good interpersonal skills and ability & desire to work as a standout colleague are a must.
Extremely self-motivated and eager to solve problems.

Hand-on experience verifying memory controller is plus.
BS or MS in electrical engineering or computer engineering.

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