Senior Design Verification Engineer

Google • Mountain View, CA

1d

About The Position

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
• Experience developing and maintaining verification test benches, test cases, and test environments.

Nice To Haves

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in low-power design verification.
• Experience with different verification techniques and methodologies including formal, GLS, UPF based Power simulations, UVM and C based testing, etc. to achieve bug-free Silicon in complex SoCs.
• Experience in ARM and RISC-V processor based DV including tool chains and C based testing.

Responsibilities

• Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or verify designs with SystemVerilog Assertions (SVA) and formal tools.
• Debug tests with design engineers to deliver design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
• Identify and write all types of coverage measures for stimulus and corner-cases.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 5,001-10,000 employees