Senior Design Verification Engineer

Mythic-posted 2 months ago
$120,000 - $225,000/Yr
Austin, TX
11-50 employees
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Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from –40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense. We’ve raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. The salary range for this position is $120,000–$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location.

  • Hands-on system-level and block-level verification.
  • Development of test plans and coverage plans.
  • Testbench development and execution using UVM or other advanced DV methodologies.
  • Creation of verification infrastructure and flows.
  • Leverage architecture models and emulation environments to help verify large AI network functionality on the design.
  • Collaborate with RTL designers and architects to verify subsystems such as scheduling fabrics, interconnects, DMA engines, and memory controllers.
  • Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • 8+ years of industry experience developing verification testbenches.
  • Knowledge of verification methodologies (UVM or similar).
  • Solid understanding of computer architecture, including datapaths, memory hierarchies, and interconnects.
  • Experience verifying one or more of the following: scheduling subsystems, high-performance interconnects, DMA engines, or memory subsystems.
  • Understanding of Verilog, SystemVerilog, and UVM.
  • Proven track record of first-pass silicon success.
  • Strong communication skills, both written and spoken.
  • Experience with emulation or FPGA prototyping for large-scale designs.
  • Knowledge of coverage-driven verification and advanced stimulus generation techniques.
  • Exposure to formal verification methods and tools.
  • Familiarity with power-aware and performance-driven verification flows.
  • Prior experience verifying AI, DSP, or other highly parallel architectures.
  • Strong scripting skills (Python or similar) for automation and infrastructure development.
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