Senior CPU Power Architect

NVIDIA•Us, CA

63d

About The Position

Are you interested for pushing the boundaries in hardware architectures for Artificial Intelligence (AI), Deep Learning (DL), autonomous vehicles, and High-Performance Computing (HPC)? NVIDIA is seeking a skilled CPU Power Architect to own and optimize CPU power efficiency across the full design cycle – from early modeling to silicon validation. You will collaborate with architecture, RTL, physical design, and validation teams to ensure our CPUs meet aggressive performance-per-watt targets. With the introduction of the Grace CPU Superchip, NVIDIA has expanded into the CPU server market, complementing our world-class GPUs and SoCs. These CPUs play a critical role in orchestrating complex workloads with exceptional performance-per-watt efficiency. The CPU architecture team is driving innovations that integrate seamlessly with NVIDIA’s broader technology stack, enabling faster AI model training, efficient data processing, and scalable cloud deployments.

Requirements

BS/MS in EE, CE, or CS or equivalent experience.
3+ years of experience working in ASIC power measurement and optimization.
Strong understanding of leakage and dynamic power in VLSI circuits
Experience with RTL and netlist power analysis tools such as Power Artist, PrimeTime PX, or equivalent.
Familiarity with CPU microarchitecture (CPU pipeline design, out-of-order execution, cache hierarchy, branch prediction) and understanding of microarchitectural power model.

Nice To Haves

Proficiency in Python for automation and data analysis.
Experience with DVFS, clock gating, power gating, and multi-voltage domain design.
Knowledge of lab instrumentation for power measurement.
Strong communication skills for cross-team technical discussions.

Responsibilities

Pre-silicon Power Estimation: Model and estimate CPU power at C-model, RTL, and netlist stages using industry-standard tools.
Power Optimization: Identify inefficiencies and drive design improvements in collaboration with architects, RTL designers, and PD engineers.
Test Development: Create targeted power characterization tests (e.g., peak power, di/dt stress patterns) for both simulation and silicon.
Silicon Validation: Measure CPU power and performance in the lab; correlate silicon results with pre-silicon estimates to refine models.
Cross-functional Collaboration: Partner with multiple engineering disciplines to achieve optimal power efficiency without compromising performance.