This individual independently plans, performs the moderately-defined responsibility for working with microarchitecture and RTL design team to implement the designs, meeting aggressive power, area and performance goals using industry standard tools/flows. Works with CPU microarchitecture team to understand specifications and design trade-offs in pipeline and structure sizing. Performs feasibilities to validate implementability, area, timing and power. Synthesizes the Verilog RTL into gate level designs and performs optimizations. Performs SynthPlace & Route on the designs using industry standard tools and delivers GDS. Optimizes the design at various stages from RTL to GDS to meet timing, power and area goals. Validates the designs for functional and electrical robustness. Acts as a strong contributor at design reviews and project meetings.