Senior CPU Design Verification DevOps Engineer

Google LLC•Austin, TX

60d•$156,000 - $229,000

About The Position

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with verification flow infrastructure or CAD.
Experience with Python or Perl scripting languages.

Nice To Haves

Experience with Linux systems and networking fundamentals.
Experience with batch job schedulers (e.g., Slurm, LSF, PBS).
Experience with major vendor Electronic design automation (EDA) tools/flows as well as emulation platforms (e.g., Palladium, Protium, Zebu).
Experience with simulation/emulation regression and compute farm management flows/tools.
Experience interfacing with both CAD and IT teams and cloud computing environments, such as Google Compute Engine (GCE).

Responsibilities

Develop and deploy tools and infrastructure to increase productivity of the Verification team.
Develop and manage large-scale regression flows for simulation, emulation, Field-Programmable Gate Array (FPGA) platforms, including automated test generation.
Assist in development and use of databases for various key information of verification metrics including fail signatures, pass/fail rates, simulator performance, etc.
Evaluate, benchmark, and integrate Electronic Design Automation (EDA) tools into our verification flows.
Show continuous improvement to our verification flows.

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