Senior CAD Engineer

Phizenix-posted 14 days ago
Full-time • Senior
Santa Clara, CA
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We’re looking for an experienced CAD Engineer to develop, enhance, and support advanced EDA environments and design automation flows for next-generation semiconductor development. In this role, you will serve as the technical bridge between Analog/AMS and Digital/ASIC Verification teams , ensuring smooth integration from schematic capture through signoff. You will own PDK integration, flow automation, compute resource optimization, and mixed-signal verification infrastructure , working closely with design engineers, IT teams, and EDA vendors to drive efficiency and silicon success.

  • Develop, maintain, and optimize CAD and EDA environments for Analog/AMS, ASIC, Photonics, and Systems teams to ensure seamless integration and productivity.
  • Define, implement, and automate design and signoff flows for custom and digital design environments.
  • Install, configure, and manage EDA tools (Cadence, Synopsys, Siemens) and FlexLM license servers .
  • Integrate and validate PDKs, technology files, and IP libraries , collaborating with foundries and third-party vendors.
  • Oversee SLURM cluster infrastructure , including job scheduling and resource allocation to improve throughput and ROI.
  • Develop automation scripts using Python, TCL, SKILL, and Bash to streamline CAD flows and minimize manual effort.
  • Manage design repositories (Git, IC Manage) and enforce best practices for version control and configuration management.
  • Troubleshoot and optimize SPICE, DRC/LVS, PEX, and EMIR issues, supporting design teams for higher performance and reliability.
  • Monitor license utilization and compute resource metrics , recommending strategies for cost-effective scalability.
  • Collaborate with EDA vendors to resolve tool issues, influence feature development, and assess new technologies.
  • Bachelor’s or Master’s degree in Electrical Engineering or Computer Science .
  • 10+ years of hands-on experience in CAD/EDA design automation , supporting analog/AMS and digital verification environments.
  • Strong expertise with Cadence Virtuoso, ADE Assembler/Explorer, and Spectre simulation environments.
  • Experience with signoff tools such as Pegasus, Quantus, and VoltusFI (or equivalent Calibre suites).
  • Proficiency in SKILL and Python scripting for design automation and productivity improvements.
  • Experience managing FlexLM license servers , including installation, configuration, and troubleshooting.
  • Hands-on experience with PDK integration for advanced FinFET nodes (e.g., TSMC N5) .
  • Proficiency with version control systems such as Git or IC Manage (gdpxl).
  • Experience with Virtuoso AMS Designer and Cadence Xcelium for mixed-signal simulation and behavioral modeling.
  • Familiarity with SLURM cluster management and high-performance computing environments.
  • Understanding of Digital RTL-to-GDSII flows , including synthesis, P&R, STA, and PV.
  • Exposure to CI/CD pipelines for CAD flow release automation and regression testing.
  • Strong written and verbal communication skills with proven ability to mentor junior engineers .
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