Senior CAD Developer, Timing and Physical Design Optimization

NVIDIA's success builds on a foundation of industry-leading hardware, achieved through extensive design optimization that combines the best of external EDA with highly optimized internal EDA tools. We are seeking an innovative CAD Software Developer with a particular interest in algorithms for gate-level timing and physical optimization, including sizing and buffering, clock skew, incremental place and route, and IR drop modeling. Understanding both software and hardware principles is key to this role. The ideal candidate will possess a constant creativity and a self-driven desire to explore and perfect fast, high-capacity software. This position offers the opportunity to work across many technical areas and see your successes directly realized in the world's best AI hardware. Developing software within a leading hardware company means focusing on the latest processes and most advanced designs without being bogged down by legacy support, niche roles, or convoluted approval processes. Our developers enjoy unusually high intellectual freedom and the ability to explore broad roles. In this role, you will invent and optimize new methods for increasing chip frequency while minimizing power consumption across a suite of internal optimization tools. These tools already outperform the industry's alternatives in high-capacity timing closure and will advance even further with your contributions. You will improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, IR drop prediction, timing calculation, power minimization, ECO routing, and incremental parasitic extraction. As part of our software engineering team, you will write a lot of code, but this role is broader than a typical CAD or EDA position. Our team owns the entire process from discovery and invention of new optimization opportunities to developing solutions and working directly with design teams to facilitate deployment.