Senior ASIC Synthesis and STA Engineer

Ciena•Atlanta, GA

About The Position

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. Ciena’s next-generation Wavelogic Digital Signal Processor (DSP) programs rely on deep technical excellence, cross-functional collaboration, and continuous innovation. This role offers the opportunity to shape the frontend implementation of industryleading ASIC technology and contribute to the methodologies that keep Ciena at the forefront of highperformance optical networking.

Requirements

B.Sc. in Electrical Engineering, Computer Engineering, or a related discipline (or equivalent experience)
Industry experience using synthesis and/or static timing analysis tools within an ASIC development environment
Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation
Familiarity with RTL design principles and hardware description languages
Ability to work effectively within multidisciplinary engineering teams and manage deliverables to project schedules

Nice To Haves

Experience with additional frontend or backend design activities such as floorplanning, Design for Testability (DFT), or place and route
Handson exposure to deepsubmicron ASIC technologies and advanced timing closure methodologies
Scripting experience (e.g., Python, Tcl, or similar) to enhance automation and debug workflows
Background supporting DSPcentric or highspeed ASIC development programs
Experience working with external EDA vendors or foundry technology teams

Responsibilities

Execute frontend implementation for assigned IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation
Develop and maintain timing constraints to support synthesis and signoff for subsystem integration
Perform logical equivalence verification between Register Transfer Level (RTL) and gatelevel netlists throughout pre and postlayout stages
Validate clock domain crossings for toplevel ASIC integration to ensure functional integrity
Create and optimize scripts, tools, and documentation that improve synthesis and static timing workflows
Implement engineering change orders (ECOs) to support iterative design refinement
Collaborate closely with ASIC integration, IP development, physical design, and external Electronic Design Automation (EDA) partners to align frontend and backend implementation activities