Senior ASIC RTL Design Engineer

Advanced Micro Devices, Inc•Santa Clara, CA

21h

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. As a member of the SBIO front‑end design and integration team, you will collaborate with architecture, IP design, physical design, and product engineering teams to develop and deliver high‑quality IP for SOC products. In this role, you will contribute to design, integration, documentation, and cross‑functional coordination to help achieve first‑pass silicon success. We welcome applicants with experience in digital design, processor architecture, and verification who enjoy solving complex technical challenges. Ideal candidates communicate clearly, work effectively in cross‑site or distributed teams, and are comfortable learning new skills as technologies evolve.

Requirements

Bachelors or Master's degree in computer engineering/Electrical Engineering or equivalent field of study.
This role is not eligible for visa sponsorship.

Nice To Haves

Background in digital IP/ASIC design and Verilog‑based RTL development.
Familiarity with the full IP design cycle, including requirements, architecture, verification, and validation.
Understanding of RTL verification, design‑quality checks, synthesis, timing closure, and post‑silicon validation.
Experience with front‑end EDA tools, sign‑off flows, and low‑power design methodologies.
Working knowledge of scripting languages such as Python or Perl.
Ability to collaborate effectively on cross‑functional teams and manage multiple technical tasks.
Ability to create clear technical documentation in English.
Understanding of semiconductor engineering terminology and digital design concepts.
Knowledge of or experience with functional design verification.

Responsibilities

Design RTL for high‑speed digital blocks, including clock, reset, and power‑related features.
Architect and implement power‑management features and low‑power RTL techniques.
Integrate IP blocks at the subsystem level and resolve inter‑IP design and integration issues.
Manage clock‑domain crossing and linting activities for IP and subsystem designs.
Collaborate with FEINT, DFT, Physical Design, and SOC teams to incorporate feedback across disciplines.
Contribute to architecture, microarchitecture, and design documentation.
Provide clear status updates and participate in team‑based problem‑solving activities.