Senior ASIC Engineer

Palo Alto Networks•Santa Clara, CA

9d•Onsite

About The Position

Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. You will own module design from specification through silicon bring-up, working with world-class verification and physical-design engineers to hit aggressive performance, power, and schedule goals.

Requirements

BS in EE, CE, or CS (MSEE or equivalent military experience preferred).
10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production.
Expert SystemVerilog RTL skills.
Proven track record of selecting, integrating, and configuring complex IP blocks for high-speed interfaces such as PCIe, Ethernet, or DDR.
Scripting proficiency (Python, C/C++, Perl, bash or tcsh).
Demonstrated strength in: Defining micro-architecture from high-level requirements.
Datapath design expertise for intricate synch/asynch digital logic.
Debugging across simulation, emulation, and silicon.
Analyzing timing, power, and area reports and driving fixes.
Excellent leadership, collaboration, and written/verbal communication.

Nice To Haves

Networking or cybersecurity domain knowledge.
Experience with search-algorithm accelerators.
Formal-verification ownership.
Hands-on silicon validation and lab bring-up.

Responsibilities

Write clear design and micro-architecture specifications.
Design SystemVerilog RTL that meets area, performance, and power targets.
Verify your blocks with simulation, emulation, formal methods, and silicon bring-up.
Collaborate with verification engineers to debug complex scenarios, close coverage, and add design-for-debug features.
Partner with physical-design teams: review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for congestion/routability.
Innovate: pilot AI-driven design or verification flows that cut schedule risk.

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