Senior ASIC DV Engineer

Broadcom • San Jose, CA

1d

About The Position

You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: Architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Using your thorough knowledge of mixed-signal simulations (AMS, Spice, etc), developing test plans and coverage metrics from specifications and writing block and chip-level tests. Debugging RTL and Gate simulations and work with design engineers to verify fixes. Writing diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. Replicating silicon bugs in simulation environments and validating fixes or SW workarounds. Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up. Evaluating latest verification methodologies and developing scripts etc. to automate verification flows. Experience understanding and verifying low power silicon for mobile applications with good knowledge of UPF low power verification flow Ability to take customer requirements to verify full chip design and architecture

Requirements

• Bachelors and 12+ years of related experience; or Masters degree and 10+ years of related experience; or PhD and 7+ years of related experience

Nice To Haves

• MS or PhD is preferred

Responsibilities

• Architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces.
• Using your thorough knowledge of mixed-signal simulations (AMS, Spice, etc), developing test plans and coverage metrics from specifications and writing block and chip-level tests.
• Debugging RTL and Gate simulations and work with design engineers to verify fixes.
• Writing diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.
• Replicating silicon bugs in simulation environments and validating fixes or SW workarounds.
• Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up.
• Evaluating latest verification methodologies and developing scripts etc. to automate verification flows.
• Experience understanding and verifying low power silicon for mobile applications with good knowledge of UPF low power verification flow
• Ability to take customer requirements to verify full chip design and architecture

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time
• The company follows all applicable laws for Paid Family Leave and other leaves of absence.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior