NVIDIA-posted 3 days ago
Full-time • Mid Level
Durham, CA
5,001-10,000 employees

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What you’ll be doing: As a key member of the Design team, you will be responsible for the implementation of GPU sub-system modules. Make architectural trade-offs based on features, performance requirements and system limitations. You are expected to own micro-architecture, implement RTL, and deliver a fully verified, synthesis/timing clean design. Support post-silicon validation activities. Work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.

  • implementation of GPU sub-system modules
  • Make architectural trade-offs based on features, performance requirements and system limitations
  • own micro-architecture
  • implement RTL
  • deliver a fully verified, synthesis/timing clean design
  • Support post-silicon validation activities
  • Work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks
  • Masters Degree (or equivalent experience) in Electrical Engineering or Computer Engineering
  • 5+ years of proven experience working on ASIC design and development
  • Experience in micro-architecture and RTL development of complex designs in Verilog
  • Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required
  • Understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug
  • Prior experience with arbiters, scheduling, synchronization & bus protocols, interconnect networks, and/or caches is desirable
  • Knowledge of PCI-Express (Gen 3 and above) or CXL protocol is very helpful; your firsthand design experience on it is a big plus
  • Python, Perl and C/C++ programming language experience desirable
  • Good debugging and analytical skills
  • Strong interpersonal skills and ability & desire to work as a great teammate
  • equity
  • benefits
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