Senior ASIC Design Engineer

NVIDIAUs, CA
Hybrid

About The Position

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. NVIDIA has developed an outstanding team stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. NVIDIA is widely considered to be one of the technology world’s most desirable employers, encouraging engineers to build solutions for customer problems and continuously crafting the fastest, most efficient GPU products that drive continuous innovation across multiple fields. The company is committed to fostering a diverse work environment and is an equal opportunity employer, valuing diversity in its current and future employees and not discriminating on various protected characteristics.

Requirements

  • A Bachelor's or equivalent experience, or a Master's degree or equivalent experience in a relevant field, with 5+ years of experience.
  • A proven hardware engineering background with a focus on VLSI and Computer Architecture.
  • Expertise in Verilog, System Verilog, or similar HDL, along with proficiency in programming languages such as Perl/Python and C/C++.
  • Solid experience with logic synthesis and timing analysis.
  • Familiarity with build and verification tools, including simulation tools like VCS, and debug tools like Debussy and GDB.
  • Experience with test bench environments for both unit and system-level verification, including random stimulus, functional coverage, and assertion-based verification methodologies.
  • Excellent debugging and analytical skills.
  • Strong interpersonal skills, with the ability to work effectively with both on-site and remote teams.

Nice To Haves

  • Knowledge of high-speed energy-efficient data paths is an advantage.

Responsibilities

  • Documenting, implementing, and delivering fully verified, high-performance, area- and power-efficient RTL to meet design goals and specifications.
  • Crafting architecture and micro-architecture, as well as conducting RTL design and synthesis.
  • Performing logic and timing verification using advanced CAD tools and semiconductor process technologies.
  • Participating in the verification of builds through sophisticated methodologies, including the development of design properties and assumptions for formal verification.
  • Collaborating closely with several ASIC development teams, ensuring seamless communication and coordination to successfully implement build requirements.

Benefits

  • equity and benefits
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