Palo Alto Networks-posted 3 days ago
$166,000 - $235,000/Yr
Full-time • Senior
Onsite • Santa Clara, CA
5,001-10,000 employees

Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. You will own module design from specification through silicon bring-up, working with world-class verification and physical-design engineers to hit aggressive performance, power, and schedule goals.

  • Write clear design and micro-architecture specifications.
  • Design SystemVerilog RTL that meets area, performance, and power targets.
  • Verify your blocks with simulation, emulation, formal methods, and silicon bring-up.
  • Collaborate with verification engineers to debug complex scenarios, close coverage, and add design-for-debug features.
  • Partner with physical-design teams: review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for congestion/routability.
  • Innovate: pilot AI-driven design or verification flows that cut schedule risk.
  • BS in EE, CE, or CS (MSEE or equivalent military experience preferred).
  • 10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production.
  • Solid experience with PCIe core integration and lab validation.
  • Expert SystemVerilog RTL skills.
  • Scripting proficiency (Python, C/C++, Perl, bash or tcsh).
  • Defining micro-architecture from high-level requirements.
  • Datapath design expertise for intricate synch/asynch digital logic.
  • Debugging across simulation, emulation, and silicon.
  • Analyzing timing, power, and area reports and driving fixes.
  • Excellent leadership, collaboration, and written/verbal communication.
  • Networking or cybersecurity domain knowledge.
  • Experience with DDR5 memory, Ethernet (IEEE 802.3), or search-algorithm accelerators.
  • Formal-verification ownership.
  • Hands-on silicon validation and lab bring-up.
© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service