10+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFET technologies Experience with and knowledge of analog/mixed-signal IP (e.g., SERDES PHY, transmitter and receiver, PLL, DDR PHY, ADCs, DACs, LDOs, etc.) Experience leading complex layout macros during the full design cycle from floorplan analysis to completion of physical design verification Great understanding of CAD flows and tools related to analog/mixed-signal layout design Experience crafting well-matched, low noise, and low power analog blocks consisting of transistors, resistors, capacitors, pad IO's, ESD structures, etc. High level of proficiency in custom, as well as standard cell-based, floor planning and hierarchical layout assembly Must understand issues of IR drop, RC delay, electro-migration, self-heating and coupling capacitance Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard methodologies, and enthusiastically work with circuit designer or layout lead for the best approach to problems High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc., reports Knowledge of CADENCE or MENTOR GRAPHICS layout tools. Excellent interpersonal skills and able to work with remote teams
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Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
Number of Employees
5,001-10,000 employees