Senior Analog Design and Layout Engineer

Cooperidge Consulting Firm•Los Angeles, CA

12h

About The Position

Cooperidge Consulting Firm is seeking a Senior Analog Design & Layout Engineer for a premier Microelectronics Commons hub in Los Angeles, CA. This is a versatile, high-impact opportunity at the heart of the national initiative to revitalize U.S. integrated circuit design. Unlike standard production roles, this position sits at the intersection of technical consulting, academic mentorship, and funded research. You will move seamlessly from schematic capture to tape-out, supporting external customers on high-performance designs while troubleshooting design-flow bottlenecks for advanced university curriculum. This is an ideal environment for a versatile engineer who thrives on diversity in process technologies (CMOS to III-V) and enjoys the intellectual challenge of teaching and research.

Requirements

Bachelor’s, Master’s, or PhD in Electrical Engineering or a related technical field is REQUIRED.
U.S. Citizenship or Permanent Residency is REQUIRED.
Minimum of 3+ years of professional experience in analog circuit design and/or physical layout.
Verification Mastery: Strong understanding of layout verification methodologies, DRC/LVS, and parasitic extraction.
Tool Proficiency: Expert-level command of Cadence Virtuoso, SPICE , and/or Mentor Graphics.
Communication: Exceptional interpersonal skills; must be able to explain complex circuit concepts to both industry customers and engineering students.

Nice To Haves

Experience with device-level, electromagnetic, or photonic component simulations.
Prior experience in a teaching, tutoring, or workshop-led environment is a significant plus.

Responsibilities

Technical Consulting: Partner with external industry customers to develop high-performance analog/digital circuit designs, providing expert guidance from schematic capture through physical implementation.
Multi-Process Design: Design and implement solutions across a wide array of technologies, including CMOS, BiCMOS, and III-V , ensuring meticulous adherence to foundry design rules.
Academic Integration: Support specialized tape-out curriculum by demonstrating advanced layout techniques and providing clinical troubleshooting for student design flows.
Full Lifecycle Verification: Lead post-layout simulation, parasitic extraction, and rigorous layout verification efforts ( DRC/LVS ) for high-impact research projects.
Research Contribution: Contribute to funded research initiatives, authoring technical design reports and layout closure documentation for both industry and academic stakeholders.
Tool Mastery: Utilize industry-standard CAD environments ( Cadence Virtuoso ) and SPICE simulators to achieve tape-out success across diverse foundry technologies.